1. Field of the Invention
The present invention relates to a data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation.
2. Description of the Related Art
Semiconductor memory devices are widely used in many electronic products and computer systems to store and retrieve data. Presently, semiconductor memory devices have become highly integrated and operate at higher speed to improve system performance. In order to enhance the operation speed of the semiconductor devices, a double data rate synchronous dynamic random access memory (DDR SDRAM) device has been developed to provide twice the operation speed of a conventional synchronous memory device. The DDR SDRAM allows data transfers on both the rising and falling edges of the system clock, and thus provides twice as much data as the conventional synchronous memory device.
As is known to one skilled in the art, the DDR SDRAM adopts a 2-bit prefetch operation to output 2-bit data to a data pad during one clock cycle. In order to prefetch more data bits, a DDR2 SDRAM and a DDR3 SDRAM have been developed. The DDR2 SDRAM adopts a 4-bit prefetch operation to output 4-bit data to a data pad during two clock cycles, and the DDR3 SDRAM adopts an 8-bit prefetch operation to output 8-bit data to a data pad during four clock cycles. As such, the data transfer rate of the DDR2 SDRAM and DDR3 SDRAM is improved by increasing the number of the prefetch bits.
In order to realize precise timing for data input/output during a high-speed operation in DDR SDRAMs including DDR2 SDRAM and DDR3 SDRAM, a data strobe signal XDQS, which is center aligned with a data input signal XDQ, is applied from a central processor or a memory controller to the memory device. FIG. 1 is a block diagram of a prior art data input section in a DDR2 SDRAM. The block diagram includes flip-flops 10, 12, and 14, and buffers 16 and 18. The buffer 16 as a data input buffer receives and buffers a data input signal XDQ, and the DQS buffer 18 receives and buffers a data strobe signal XDQS for use within the DDR2 SDRAM. The buffered strobe signal XDQS is designated as the signal DQS, which is used to “clock in” or “strobe” data bits to be written into the memory cells (not shown).
FIG. 2 is a timing diagram illustrating a general write operation of the data input section of FIG. 1. Referring to both FIGS. 1 and 2, a “write” command is issued in synchronization with an external clock signal XCLK applied from a memory controller (not shown). After a predetermined time, the external data strobe signal XDQS is applied to the buffer 18 to generate an internal strobe signal DQS. The strobe signal DQS is delayed or phase-shifted by the buffer 18 as shown in FIG. 2. Data bits D0, D1, D2, and D3 in the data signal XDQ are serially inputted to the buffer 16. Thereafter, the flip-flop 10 receives internal data IDQ sequentially output one-bit by one-bit from the buffer 16 and outputs a signal N1 in synchronization with a rising edge of the strobe signal DQS.
Thereafter, the flip-flop 14 receives the signal N1 and provides data bit D0 to the memory cell in synchronization with a falling edge of the strobe signal DQS. Similarly, the flip-flop 12 receives the internal data IDQ from the data buffer 16 and provides data bit D1 to the memory cell in synchronization with a falling edge of the strobe signal DQS.
After finishing the write operation, the external data strobe signal XDQS enters a tri-stage condition after the completion of a postamble time 20. After the postamble time 20, the state of XDQS is no longer guaranteed and a ringing may start. Such ringing on the strobe signal XDQS may cause false data to be written into the memory cells because the postamble ring may be incorrectly recognized by the flip-flops as valid data clocking edges of the strobe signal DQS.
In order to avoid false data being written because of the postamble ringing phenomenon in the write operation in the DDR SDRAM, there is a need to provide a method and an apparatus to solve the above-described problem.